PIC18F4539-I/ML【PDF 205/322 页】IC MCU FLASH 12KX16 EE A/D 44QFN

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2002 Microchip Technology Inc.

Preliminary

DS30485A-page 281

PIC18FXX39

TABLE 23-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

100

THIGH

Clock high time

100 kHz mode

4.0

—

PIC18FXXX must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

PIC18FXXX must operate at a

minimum of 10 MHz

SSP Module

1.5 TCY

—

101

TLOW

Clock low time

100 kHz mode

4.7

—

PIC18FXXX must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

PIC18FXXX must operate at a

minimum of 10 MHz

SSP Module

1.5 TCY

—

102

SDA and SCL rise

time

100 kHz mode

—

1000

400 kHz mode

20 + 0.1 CB

300

CB is specified to be from

10 to 400 pF

103

SDA and SCL fall

time

100 kHz mode

—

1000

VDD

≥ 4.2V

400 kHz mode

20 + 0.1 CB

300

VDD

≥ 4.2V

TSU:STA

START condition

setup time

100 kHz mode

4.7

—

Only relevant for Repeated

START condition

400 kHz mode

0.6

—

THD:STA

START condition hold

time

100 kHz mode

4.0

—

After this period, the first clock

pulse is generated

400 kHz mode

0.6

—

106

THD:DAT

Data input hold time

100 kHz mode

—

400 kHz mode

0.9

107

TSU:DAT

Data input setup time 100 kHz mode

250

—

(Note 2)

400 kHz mode

100

—

TSU:STO

STOP condition

setup time

100 kHz mode

4.7

—

400 kHz mode

0.6

—

109

TAA

Output valid from

clock

100 kHz mode

—

3500

(Note 1)

400 kHz mode

—

110

TBUF

Bus free time

100 kHz mode

4.7

—

Time the bus must be free

before a new transmission can

start

400 kHz mode

1.3

—

D102

Bus capacitive loading

—

400

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of

the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement TSU:DAT

≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.

TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is

released.

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